系统与基础设施cs.virginia.edu编辑精选
没有时钟的计算机
Computers Without Clocks – Ivan Sutherland (2002) [pdf]
2016 — 2020，它一次次回到首页
黑点是上首页（≥ 50 分）的那次投稿，空心点是没冲上去的投稿，点越大分数越高。
导读
这是 Ivan Sutherland 2002 年的文章《Computers Without Clocks》，讨论用异步、无全局时钟的电路取代传统同步时钟设计的可能性。文章指出时钟必须迁就最慢路径、分发困难且耗能，因此无时钟计算在速度和功耗上可能有优势，但也带来设计与验证上的挑战。
为什么经久不衰：它清晰阐述了无时钟计算的核心权衡；二十多年后评论区仍在讨论工业界为何没有广泛采用，是理解异步电路潜力与现实障碍的经典入口。
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无时钟设计有潜力，但工程门槛高、工具链缺失、工业界迁移成本巨大，因此短期难成主流。
我是这个领域的博士生，可以谈谈现状。相关术语包括 clockless、self-timed、delay-insensitive、latency-insensitive、quasi delay-insensitive（QDI）、speed independent、asynchronous、bundled-data。无时钟电路有多种时序假设：QDI 最保守、假设最少；bundled-data 最不保守，实际上类似时钟门控。无时钟流水线总比时钟化流水线慢，面积约为两倍；但它更灵活，可以跳过不必要的计算，整体上可能显著提高吞吐并降低能耗，不过需要非常仔细的设计和完全不同的体系结构。VLSI 工业普遍缺乏无时钟设计教育，工具也很差；我见过许多把同步架构改成无时钟的项目，结果总是性能更差。对现有 VLSI 公司来说，重做工具链要花数十亿美元，而且只带来一次性收益，所以大公司短期内大概不会推出无时钟处理器；它们现在似乎在收购异步初创公司然后关掉。
nbingham查看英文原文
Heyo, I'm a PhD student in the field. I figured I can talk about its current status. First, here are various search terms: clockless, self-timed, delay-insensitive, latency-insensitive, quasi delay-insensitive (QDI), speed independent, asynchronous, bundled-data There are a wide variety of clockless circuits that each make their own timing assumptions. QDI is the most paranoid, making the fewest timing assumptions. Bundled-data is the least paranoid (its effectively clock-gating). A clockless pipeline is always going to be slower than a clocked one and requires about 2x the area. However, clockless logic is way more flexible, letting you avoid unnecessary computation. Overall, this can mean significantly higher throughput and lower energy, but getting those benefits requires very careful design and completely different computer architectures. Most of the VLSI industry is woefully uneducated in clockless circuit design and the tools are terribly lacking. I've seen many projects go by that make a synchronous architecture clockless, and they have always resulted in worse performance. What this means is that it would take billions of dollars for current VLSI companies to retool, and doing so would only give them a one-time benefit. So, you probably won't see clockless processors from any of the big-name companies any time soon. What they seem to be doing right now is buying asynchronous start-ups and shutting them down. As of the 90nm technology node, its not possible to be switching all of the transistors on chip without lighting a fire. This mean that the 2x area requirement is not much of a problem since a well-designed clockless circuit only needs to switch 25-50% of them at any given time. Also since 90nm, switching frequencies seem to have plateaued with a max of around 10 GHz and typical at around 3 GHz. When minimally sized, simple clockless pipelines (WCHB) can get at most 4 GHz and more complex logic tends to get around 2 GHz (for 28nm technology). Leakage current has become more of a problem, but it's a problem for everyone. There is a horribly dense wikipedia page on QDI, but it has links to a bunch of other resources if you are curious.
从业者指出无时钟设计未进入主流，漏电功耗和巨额工具链投资是现实障碍。
我设计半导体已经 23 年。这篇文章是 17 年前发表的，而在我整个职业生涯中从未见过无时钟设计。大约三分之一到一半的功耗是漏电，我看不出无时钟设计如何帮助解决这一点；我们会动态降低电压，并为未使用或较少使用的部分设置电源岛。nbingham 关于工具的观点很好：我们在工具流程上投入了数十亿美元，除非看到无时钟设计在某些可测量方面更好的证据，否则不会抛弃它。
lizknope查看英文原文
I've been designing semiconductors for 23 years. This article is 17 years old and I haven't seen any clockless designs in my professional experience in all of that time. About 1/3 to 1/2 the power usage is leakage and I don't see how a clockless design will help that. We dynamically lower the voltage and have power islands for unused or lesser used portions. nbingham makes a great point about the tools. We have invested billions of dollars in tool flows. We are not going to throw that away until we see some proof that clockless designs are better in some measurable ways.
流水线已缓解最慢路径限制，同步设计在处理亚稳态和跨时钟域上更简单。
文章说，同步芯片的时钟节奏必须慢到能容纳芯片电路中最慢的动作；如果某个电路需要十亿分之一秒完成操作，芯片就不能快过 1GHz。我还没读完整篇文章，但流水线正是为解决这个问题而出现的。同步电路还有一个很好的性质：能处理亚稳态。合并不同时钟域是噩梦，我很想知道他们打算如何解决类似问题。
vvanders查看英文原文
"First, asynchrony may speed up computers. In a synchronous chip, the clock’s rhythm must be slow enough to accommodate the slowest action in the chip’s circuits. If it takes a billionth of a second for one circuit to complete its operation, the chip cannot run faster than one gigahertz." Haven't read the whole article yet but pipelining was made specifically to address this exact problem. Also synchronous circuits have a nice property of dealing with metastability. Merging different clock domains is a nightmare and I would love to know how they plan on solving similar issues.
AMULET 是异步 ARM 处理器的重要历史实例。
Steve Furber（BBC Micro 的创造者、ARM CPU 的共同设计者）领导曼彻斯特大学团队设计了一款 ARM CPU 的异步版本，叫 AMULET。
trollied查看英文原文
Steve Furber (creator of the BBC Micro, and co-designer of the ARM CPU) headed up a team at Manchester University that designed an asynchronous version of the ARM CPU, called AMULET. Details: http://apt.cs.manchester.ac.uk/projects/processors/amulet/AMULET3_uP.php https://en.wikipedia.org/wiki/AMULET_microprocessor
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