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程序员关于 CPU 缓存的误区（2018）
Myths Programmers Believe about CPU Caches (2018)
2018 — 2025，它一次次回到首页
黑点是上首页（≥ 50 分）的那次投稿，空心点是没冲上去的投稿，点越大分数越高。
导读
这篇文章梳理了程序员对 CPU 缓存的常见误解，例如认为缓存一致性协议能自动解决所有并发问题、缓存行总是按预期加载等，并结合 MESI 协议、内存屏障和伪共享等概念逐一澄清。文章以 x86 为主展开讲解，帮助读者理解硬件在底层对内存访问的真实行为。
为什么经久不衰：CPU 缓存的误解直接影响并发正确性与性能优化，这篇文章用清晰的讲解破除常见迷思，多年后仍是理解现代硬件内存模型的优质入门材料。
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推荐系统学习缓存一致性的经典教材，并指出多数程序员更应关注数据竞争与顺序一致性
如果你确实需要关注缓存一致性，我强烈推荐《A Primer on Memory Consistency and Cache Coherence》这本书。从更宏观的视角理解一致性的细节，比零散读一堆博客容易得多。这本书很易读，澄清了我大部分误解，还提供了一套讨论一致性问题的通用词汇。不过缓存一致性对大多数程序员并不那么重要：每种语言都在缓存之上提供了抽象，几乎都采用“无数据竞争则顺序一致”的模型。理解数据竞争和顺序一致性比理解缓存更重要，因为编译器/运行时对代码的改动比 CPU 更自由（除非你在用 DEC Alpha 这类架构）。但如果你在写操作系统、虚拟机管理程序或编译器等直接接触汇编的场景，就需要扎实掌握缓存一致性。
strstr查看英文原文
If cache coherence is relevant to you, I strongly recommend the book “A Primer on Memory Consistency and Cache Coherence”. It’s much easier to understand the details of coherency from a broader perspective, than an incremental read-a-bunch-of-blogs perspective. I found that book very readable, and it cleared up most misconceptions I had. It also teaches a universal vocabulary for discussing coherency/consistency, which is useful for conveying the nuances of the topic. Cache coherence is not super relevant to most programmers though. Every language provides an abstraction on top of caches, and nearly every language uses the “data race free -> sequentially consistent”. Having an understanding of data races and sequential consistency is much more important than understanding caching: the compiler/runtime has more freedom to mess with your code than your CPU (unless you are on something like the DEC Alpha, which you probably aren't). If you are writing an OS/Hypervisor/Compiler (or any other situation where you touch asm), cache coherence is a subject you probably need a solid grasp of.
文章偏 x86，ARM 等更宽松架构需要更多屏障，acquire/release 模型正成为行业趋势
这是一篇不错的高层次缓存一致性入门介绍……不过是针对 x86 的。ARM 系统的内存模型更宽松，需要更多内存屏障。只要正确使用锁等同步原语，内存屏障就会被正确处理。至少出于性能考虑，了解底层机制是有益的，尤其是写无锁数据结构时，你需要自己把屏障放在合适的位置。我认为 acquire/release 一致性模型在未来会越来越重要：PCIe 4.0 已有支持迹象，ARM、POWER 加了相关指令，CUDA 也在引入。随着高性能系统越来越宽松，acquire/release 正迅速成为标准模型。
dragontamer查看英文原文
A good, introductory, high-level overview of what is going on with cache coherence... albeit specific to x86. ARM systems are more relaxed, and therefore need more barriers than on x86. Memory barriers (which also function as "compiler barriers" for the memory / register thing discussed in the article) are handled as long as you properly use locks (or other synchronization primitives like semaphores or mutexes). Its good to know how things work "under the covers" for performance reasons at least. Especially if you ever write a lock-free data-structure (not allowed to use... well... mutexes or locks), so you need to place the barriers in the appropriate spot. ------ I think the acquire/release model of consistency will become more important in the coming years. PCIe 4.0 is showing signs of supporting acquire/release... ARM and POWER have added acquire/release model instructions, and even CUDA has acquire/release semantics being built. As high-performance code demands faster-and-faster systems, the more-and-more relaxed our systems will become. Acquire/release is quickly becoming the standard model.
补充 DMA 与 CPU 缓存不一致的问题及几种应对方案
文章没提到的一点是：DMA 通常与 CPU 缓存不保持一致性。如果你使用 DMA 设备（内存↔设备或内存↔内存拷贝），可能遇到 DMA 和 CPU 看到不同值的情况。解决办法要么手动失效缓存并与 DMA 同步（如通过中断），要么请求操作系统把该内存区域设为完全不缓存；某些情况下，如果 DMA 只读内存，也可以用写穿透缓存策略。
sherincall查看英文原文
One thing not mentioned here (nor in previous discussions of the article, it seems) is that DMA is typically not coherent with the CPU caches. This is kinda visible from the little diagram at the top, with the disk sitting on the other side of the memory, but it should be explicitly spelled out. If you're using a DMA device (memory<->device or memory<->memory copies), you might end up in a state where the DMA and the CPU see different values. This usually means data transfer to/from a Disk or GPU, though other peripherals might use it too. Your options here are either to manually invalidate your caches and synchronize with the DMA (e.g. via interrupts), or to request from the OS that the given memory section be entirely uncached; or in some cases, you can get away with a write-through cache policy, if the DMA is only ever reading the memory.
分享一篇关于缓存与循环顺序对性能影响的实测分析
感兴趣的话，我在 2014 年做过一个关于 CPU 缓存和 for 循环的简单分析，指出了一些陷阱。希望对人有帮助，当同事问我为什么调整循环和函数顺序，或者问我如何在不改功能的情况下提速时，我常把这个链接发给他们。
lettergram查看英文原文
For those interested (in 2014!) I did a rather simple analysis of CPU caches and for loops to point out some pitfalls: https://austingwalters.com/the-cache-and-multithreading/ Hope it helps someone, I tend to link it to my co-workers when they ask me why I PR'd re-ordering of loops & functions OR when they ask how I get speedups without changing functionality.
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