系统与基础设施excamera.com
J1 Forth CPU
The J1 Forth CPU
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导读
这是 James Bowman 的 J1 项目页面：一个面向 FPGA 的栈式（Forth）CPU，用约 200 行 Verilog 实现，带 16KB RAM 的完整系统可以轻松放进一块小型 Xilinx FPGA。页面介绍了它的设计思路与实现细节，并附有面向 Lattice iCE40 的精简版本。
为什么经久不衰：它把「CPU 可以有多简单」这件事展示得淋漓尽致，是理解 Forth、栈式机器与软硬件边界的一份经久不衰的入门材料。
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Forth 处在机器码与常规编译器之间的独特抽象层，本质是带运行时符号表的栈式汇编。
J1 是一个小的（200 行 Verilog）、基于栈的 CPU，专为 FPGA 设计。一个带 16KB RAM 的完整 J1 很容易放进小型的 Xilinx FPGA。我很久以前觉得 Forth 只是又一门编程语言，当时并不欣赏它，因为没搞懂它在现代计算的抽象层级中处于什么位置——那时我还没写过编译器。现在我要说 Forth 为何如此美妙：在抽象层面，晶体管最低、Lisp 一类最高、多数编译器居中，而 Forth 是机器语言之上的一步，却在大多数编译器之下。如果你曾从下往上（从汇编到编译器）而不是从上往下（如大学课本《龙书》那样）写编译器，就会明白这一点。Forth 大致相当于给你的汇编代码加上一张运行时的符号（关键字）查找表，让地址（也就是标签、函数、过程、方法）能在运行时动态执行，并围绕这个概念构建一个解释器／栈机器。当然还有更多内容，但基本思想就是如此。
peter_d_sherman查看英文原文
>"J1 is a small (200 lines of Verilog) stack-based CPU, intended for FPGAs. A complete J1 with 16Kbytes of RAM fits easily on a small Xilinx FPGA. PDS: A long time ago, I thought that Forth was "just another computer programming language", but back then, I had no appreciation for it, because I didn't understand where it fits in on the abstraction hierarchy that we call modern day computing... I didn't have this appreciation, at the time, because I had not worked on writing compilers at the time... Now, let me explain to you why Forth is so gloriously wonderful! You see, in terms of abstraction, where transistors are the lowest level, and Lisp, and Lisp-like languages are the highest, and most compilers are somewhat mid-level, Forth is the next step up above machine language -- but a step below most compilers! You'd know this, you'd derive this, if you ever tried to write a compiler from the bottom up (going from assembly language to a compiler) rather than from the top down (what is taught about compiler construction in most University CS classes, i.e., the "Dragon Book", etc.) See, Forth is sort of what happens when you add an at-runtime symbol (AKA, "keyword") lookup table to your assembler code, such that addresses (AKA "labels", AKA, "functions", AKA "procedures", AKA "methods") can be dynamically executed at runtime, and you create an interpreter / stack-machine -- around this concept. There's a little bit more to that of course, but that's the basic idea. Then you derive Forth! That's why Forth is so gorgeous and brilliant! And so aesthetically pleasing, because of it's small size, yet amazing functionality! And why you don't need big, complex CPU's to run it! It exactly follows the "Einsteinian mantra" of "As simple as possible, but not simpler!" Anyway, thanks again for your great work with the J1 Forth CPU!
补充了更小、更易上手的 J1A 版本及配套文章和视频。
也值得看看 James 为 Lattice iCE40 做的简化版本。
Cieplak查看英文原文
Also worth checking out James’s simplified version designed for the Lattice iCE40 [1][2]. [1] https://www.excamera.com/sphinx/article-j1a-swapforth.html [2] https://youtube.com/watch?v=rdLgLCIDSk0
栈式架构能显著简化 CPU 的微代码设计。
大学时有一门课要求设计 CPU。我从普通的寄存器式设计入手，最后转向了栈式设计。那是我在那个项目里做出的最好决定之一，它极大简化了微代码，也让编程变得简单有趣。
rbanffy查看英文原文
In college, one of our assignments was to design a CPU. I started with a plain register-based one, but ended up moving to a stack-based design. It was one of the best decisions I made in the project, simplified the microcode enormously and made programming it easy and fun.
Forth 栈式思想在 Chuck Moore 的 GreenArrays 多计算机芯片上被推向极致：无时钟、极低功耗。
另一款由 Forth 之父 Chuck Moore 等人设计的 Forth CPU：GreenArrays。一平方厘米的芯片上有 144 个核心。每个核心都有自己的小数据栈和控制栈，是完整的独立计算机（所以更准确的说法是「多计算机芯片」而非「多核」）。核心之间通过通信端口交流：写端口会挂起该核心，直到对端读取该值，反之亦然（类似 Go 语言的 channel）。其他有趣特性包括：可从多个端口读取（类似 Go 的 select）并能直接从端口执行指令；细粒度能耗控制——若地址（端口或 I/O 引脚）不活跃，读写指令会在操作中途自动挂起，只消耗晶体管漏电，等地址活跃再恢复；无时钟——大多数计算设备靠时钟同步，空闲待命时时钟生成与分发仍在大量耗能，而该架构干脆省略时钟以省电省时。
avodonosov查看英文原文
Another Forth CPU by the Forth creator Chuck Moore and colleagues: http://www.greenarraychips.com/. It's has 144 cores on a square centimeter chip. Each core is equipped with its own little data and control Forth stacks, making it a fully fledged independent computer (that's why the more precise term is "multi-computer chips" rather than "multi-core"). The cores talk to each other via communication ports. Writing to a port suspends the core until the peer reads the value. And vice-versa. (similar to channels in Go language). Some other interesting properties (quoting the docs): A computer can read from multiple ports [corresponds to Go's select] and can execute instructions directly from those ports. FINE GRAINED ENERGY CONTROL: ... The read or write instruction is automatically suspended in mid-operation if the address [one or more of communication ports and I/O pin] is inactive, consuming energy only due to transistor leakage currents, resuming when the address becomes active. NO CLOCKS: Most computing devices have one or more clocks that synchronize all operations. When a conventional computer is powered up and waiting to respond quickly to stimuli, clock generation and distribution are consuming energy at a huge rate by our standards, yet accomplishing nothing. This is why “starting” and “stopping” the clock is a big deal and takes much time and energy for other architectures. Our architecture explicitly omits a clock, saving energy and time among other benefits. http://www.greenarraychips.com/home/documents/greg/PB002-100822-GA-Arch.pdf
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