系统与基础设施danluu.com
Verilog 很怪
Verilog Is Weird
2013 — 2022，它一次次回到首页
黑点是上首页（≥ 50 分）的那次投稿，空心点是没冲上去的投稿，点越大分数越高。
导读
Dan Luu 的这篇文章探讨为什么硬件开发如此困难，指出 Verilog 等硬件描述语言设计怪异、工具链落后，行业对软件工程实践（如 lint 工具）的采用也远落后于软件行业。文章还分析了硬件行业依赖多年经验、年轻工程师成长缓慢等现象。
为什么经久不衰：它从从业者视角揭示了硬件开发与软件开发的根本差异和行业积弊，多年来反复引发讨论，对理解软硬件文化差异仍有参考价值。
HN 评论精选
难点在于数字逻辑基础而非语言本身，并纠正了文中异步复位的例子
我认为学习芯片设计真正难的不是语言，而是其他东西——理解何时/如何使用存储（触发器）和组合逻辑，以及如何处理同时发生的事情。首先需要对数字逻辑（尤其是流水线）有扎实的理解，之后再去学 Verilog 如何把这些概念映射到语言中。文中例子里的异步复位请忽略——它在现实中往往是时序噩梦，应该用同步复位。
Taniwha查看英文原文
I think that really the hard part of learning to design chip stuff really is other stuff - understanding where/how to use storage (flops) and combinatorial logic - and simultaneity: how to handle things that happen at the same time. Initially you really need a strong understanding of digital logic (not a language), in particular pipelines. Once you have that stuff in your head you can turn to verilog (or vhdl or whatever) and learn how to map these ideas into the language In System Verilog it's easy this is the only way to reliably make synthesisable flops: bit a, b; always @(posedge clk) a <= b; And you can make combinatorial logic 2 ways: wire c; bit d; assign c = a&b; always @(*) d = a&b; They'll make the same gates, notice the use of = vs <=, you typically use the always when you want something more complex "always X" just means loop waiting for X, '*' means "anything important changes" That's it, the most important concepts you have to get your head around, everything else is just this at scale - also please ignore the async reset in the "Verilog is Weird" example - they tend to be timing nightmares in the real world, use a synchronous reset instead. One more thing - Verilog is an early object oriented language - modules are objects - but they are static, the entire design can be elaborated at compile (or synthesis) time - why? because you can't new or malloc more gates on the fly on a real chip - almost everything in verilog is static by design (it does support local variables in functions but anything that's vaguely recursive wont make gates in synthesis)
文章部分内容已过时，现代硬件公司普遍使用 lint 等检查工具
这篇文章似乎有些过时了，尤其惊讶于提到硬件公司不用 lint 工具——Lint、逻辑等价性检查、CDC 检查等都是硬件设计必备的检查手段。我同意 Verilog 有很多坑，但头脑中知道代码会生成什么样的硬件并不是坏事，这正是让设计跑到 4GHz 而不是 100MHz 的关键。
tails4e查看英文原文
Any idea when this was written? It seems a bit out dated, and I'm especially surprised at the mention of hardware companies not using linters, that seems insane to me. Lint, Logic Equalivance, CDC, etc are all absolutely required sanity checks on hardware design, irrespective of the language. Also SystemVerilog is quite esperessive. I definitely agree Verilog has many pitfalls you basically get used to and know to avoid, but I don't agree that knowing in your head the hardware that will be generated is a bad thing. Knowing how the hardware will be constructed from your code is key to getting it running at 4Ghz instead of 100Mhz. What your code will infer could be less or more area efficient, etc. Modern synthesis tools do help map sometimes inefficient code to the right hardware, but still knowing what it should create is a positive thing.
Verilog 难是因为被误用为编程语言，正确流程是先设计硬件再编码
Verilog 显得“难”是因为人们常把它当编程语言来用，而这在大多数情况下毫无意义。正确的做法是先设计好硬件，再用 Verilog 把它写出来（相比设计本身，写代码是轻而易举的部分）。实际上这篇文章用的 motivating example 本身就不合理。
tonmoy查看英文原文
Verilog seems "hard" because people often use it in a similar fashion to a programming language, and in most cases that does not make any sense. The proper way to use it is to design the hardware, then code it up using verilog (which is trivial compared to the actual design). In fact in terms of time spent on design, the actual coding part does not take much time at all. In fact, this very article uses a motivating example that does not make any sense.
硬件行业论资排辈严重，靠年限而非能力晋升，消磨年轻人
作者说硬件行业里资深者居多，我作为 CPU 验证工程师深有体会：这个行业的职业机会完全取决于工作年限。ARM 曾公开宣称毕业生要工作两年后才被期望“擅长某件事”。如果你想凭能力而非简历年限晋升，别选硬件行业。这种环境常常消磨年轻工程师的热情，而且创业公司太少，好的工程实践也不受重视。
CPU_Verif查看英文原文
I'll throw in my opinion for this. The author states how its routine for people to be older in the Hardware Industry. I work as a Verification engineer for a CPU project. From what I see, every company in this sector works off of years of experience. Even if you are god's gift to the world of CPU design, the career options available to your are linked to the years you have worked. I recently attended a presentation by ARM, where they boasted of this quote "At ARM, we don't really expect our graduates to be able to do anything until they're about 2 years into their careers, at which point they're expected to be decent at something" And they boasted of it! To a theater full of CS students. And this was a 35 year old line manager making the comment. If you want a career where you can rise based on merit, and not the numbers of years on your CV, don't pick hardware. I've seen it as an insider, the occasional "kid" comment being thrown around(ARM), designers refusing to work with junior verif staff(imagination tech), people who have written a project from scratch over 2 years not given tech lead roles as the project grew, etc. Such an enviroment quite often bleeds younger engineers. It saps desire and motivation. Because there are so few startups, good practices don't matter. Here's some conversations I've had: "We don't need to write tests for our software ISG, its a waste of time" "What is wrong with me writing an extension to the software as a special case? It only executes that code if the username is me" "We don't do training for new people". I routinely see younger engineers with 3-4 years of experience try and spin out of CPU/Hardware and into Software.
历次讨论
同类还值得读
TTY 揭秘（2008）
The TTY demystified (2008)
经典文章深入剖析了 Unix/Linux 中 TTY 子系统的工作原理，包括线路规程、终端驱动、信号与控制字符等机制。
系统与基础设施上首页 11 次 · 2009–2025linusakesson.net编辑精选为什么 GNU grep 这么快
Why GNU grep is Fast
FreeBSD 邮件列表上一篇广为流传的帖子，解释 GNU grep 为什么快：核心在于 Boyer-Moore 字符串搜索算法配合精心优化的内部循环和 I/O，让程序在搜索时“…
系统与基础设施上首页 9 次 · 2010–2022lists.freebsd.orgXplain：为普通人讲解 X11
Xplain – Explaining X11 for the rest of us
《Xplain》是作者（HN 用户 Jasper_）写的一系列 X11 长文，用他在浏览器中重建的 X11 绘图模型做交互演示，讲解 X11 的绘图模型与窗口系统设计。
系统与基础设施上首页 6 次 · 2013–2020magcius.github.io编辑精选旋风教程：为 Linux 创建极小 ELF 可执行文件（1999）
A Whirlwind Tutorial on Creating Really Teensy ELF Executables for Linux (1999)
breadbox 写于 1999 年的经典教程，主题是如何为 Linux 手工构造并裁剪出体积极小的 ELF 可执行文件。
系统与基础设施上首页 6 次 · 2007–2025muppetlabs.comPostgreSQL 内部原理
The internals of PostgreSQL
《The Internals of PostgreSQL》是一本免费在线书籍，系统讲解 PostgreSQL 的内部实现，包括查询处理、并发控制、WAL、缓冲区管理等核心机制。
系统与基础设施上首页 5 次 · 2017–2025interdb.jp编辑精选