系统与基础设施lighterra.com编辑精选
现代微处理器：90 分钟指南
Modern Microprocessors – A 90-Minute Guide (2001-2016)
2011 — 2021，它一次次回到首页
黑点是上首页（≥ 50 分）的那次投稿，空心点是没冲上去的投稿，点越大分数越高。
导读
这是一篇由 Lighterra 发布的现代微处理器入门长文，用约 90 分钟的阅读量讲解了 2001–2016 年间 CPU 架构的核心概念，包括缓存、乱序执行、寄存器重命名等。文章多次登上 Hacker News 首页，被读者认为是比课堂讲解更清晰、且解释了设计背后取舍原因的优质资料。
为什么经久不衰：它用平实的语言讲清了缓存、乱序执行、寄存器重命名等核心概念，并补上了教科书常缺的'为什么这样设计'的取舍分析，多年后仍是理解现代 CPU 的最佳入门读物之一。
HN 评论精选
寄存器重命名本质上是动态物理寄存器分配，用来消除数据冒险
对硬件人士来说这可能是显而易见的，但理解寄存器重命名的那一刻对我很有启发。我以前（错误地）以为 rdi、rsi 等寄存器对应物理存储位。现在我明白 rdi、rsi 等不过是干扰图中的压缩节点标识符。理想情况下我们应有无限个寄存器：每条指令从之前的寄存器读取并输出到新寄存器，这样就不会复用任何寄存器，也就没有数据冒险。可惜 ISA 的位数有限，必须复用寄存器。寄存器重命名就是从压缩形式重建近似无限寄存器的干扰图，再映射到有限（但更大）的物理寄存器集上的技术。'寄存器重命名'这名字起得不好，'动态物理寄存器分配'更贴切。
ridiculous_fish查看英文原文
This is no doubt obvious to hardware folks, but one enlightening moment is when I came to understand register renaming. Previously I had the (wrong) idea that rdi, rsi, etc corresponded to physical bits. Register renaming involved some exotic notion where these registers might be saved and restored. Now I understand that rdi, rsi, etc. are nothing but compressed node identifiers in an interference graph. Ideally we'd have infinite registers: each instruction would read from previous registers and output to a new register. And so we would never reuse any register, and there'd be no data hazards. Alas we have finite bits in our ISA, so we must re-use registers. Register renaming is the technique of reconstructing an approximate infinite-register interference graph from its compressed form, and then re-mapping that onto a finite (but larger) set of physical registers. Mostly "register renaming" is a bad name. "Dynamic physical register allocation" is better.
文章遗漏了 DMA 与缓存交互（如 DDIO）等重要的 I/O 相关内容
文章漏了一些涉及 DMA 的 I/O 内容。过去 PCI 设备的 DMA 直接读写 DRAM，CPU 访问这些数据时延迟很高。网络处理器找到了简单解法：DMA 直接进缓存而非 DRAM，这降低了 I/O 延迟并简化了 I/O 一致性。Intel 在内存控制器和 PCIe 集成到同一芯片后也采用了这一方案，称为 DDIO，如今 Intel Xeon 靠它支持 100G 以太网。另一个话题是 x86 的 DMA 是缓存一致的（无需在 I/O 前刷缓存，而 ARM 上我得这么做），这对驱动开发者来说太棒了。我认为未来会涉及对缓存共享的更好控制，比如限制线程只能使用部分缓存，避免干扰其他线程。
jhallenworld查看英文原文
There are some missing I/O things involving DMA. In the old days, DMA from (say) a PCI device would go directly to and from DRAM. This incurs a high latency if the CPU needs to access this data. Network processors found a simple solution: DMA goes to the cache, not the DRAM. This reduces the I/O latency to the processor and simplifies I/O coherency. I know Cavium's NPs rely on this. Intel picked this up for server and desktop processors once both the memory controller and PCIe were integrated on the same die. They called it DDIO: https://www.intel.com/content/www/us/en/io/data-direct-i-o-technology.html You can support 100 G Ethernet with Intel Xeon processors these days due to this. Another story is how DMA in the x86 world is cache coherent (no need to use uncached memory or flush before starting an I/O operation- which I have to do it in ARM). This is awesome from a device driver writer's point of view and is the result of having to support old operating systems from the pre-cache days. I think the future will involve better control of how cache is shared. For example, if you know a program is going to access a lot of memory, but does not need to keep it around for a long time, it will as a side effect, eject useful data from the cache. Better would be to declare that a thread should only be able to use some fraction of the cache so that it does not interfere with other threads so much.
文章对缓存和设计取舍的讲解比课堂材料更清晰，尤其难得地解释了'为什么'
写得非常好。我 2003 年从 ECE 专业（主攻 VLSI 和计算机体系结构）毕业，之后转做软件，这篇文章既是很好的复习，也讲解了当时还没普及的新技术。我尤其喜欢他对缓存工作原理及不同类型（直接映射 vs n 路组相联）的讲解——记得当年在学校花了好久才真正理解缓存，这里的解释比我课上见过的任何材料都清晰。最让我印象深刻的是对各设计优缺点和各种取舍的讨论，'为什么这样设计'往往是被略去的部分。
kelnos查看英文原文
Really good read. I graduated from an ECE program (with a focus on VLSI and comp arch) in 2003, but went straight to software after that, so this was a great refresher for me, as well as explaining some of the newer stuff that hadn't been in use then. I especially liked how he explained how caches work, and the different types (direct-mapped vs. n-way associative). I remember it took me a while back in school to really grok caching, but the explanation here was clearer than anything I ever saw in class. Overall I was most impressed by the discussions of the pros and cons of each of the designs and the various tradeoffs involved. Often the "why did they do it this way?" is left out. Heh, perhaps I just read it faster because I have some familiarity already, but I got through it in about 45 minutes.
质疑文中'x86 动态解码为内部 RISC 指令'的说法可能不准确
在 @rygorous 关于 CPU 架构的精彩 Twitch 直播中，他说 x86 架构动态解码成内部 RISC 指令基本上是个迷思。因此我对这篇文章整体持一点怀疑态度，因为我自己不够懂，无法逐条验证。
ecuzzillo查看英文原文
So, in @rygorous's excellent Twitch streams about CPU architecture (first one here: https://www.youtube.com/watch?v=oDrorJar0kM), he said that it was basically a myth that x86 architectures dynamically decoded into internal RISC instructions. I am thus a little skeptical of the article in general, since I don't know enough myself to verify each thing.
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