编程与软件工程randomascii.wordpress.com
清零寄存器那些令人惊讶的微妙之处
The surprising subtleties of zeroing a register (2012)
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导读
这篇文章讲的是 x86 汇编中"把寄存器清零"这一看似平凡的操作背后的微妙之处：为什么编译器偏爱用 xor reg,reg 而不是 mov reg,0，以及寄存器重命名如何让清零几乎不消耗执行资源。作者还通过基准测试比较了不同清零指令的实际表现。
为什么经久不衰：它用一个极小的例子揭开了现代乱序 CPU 的核心机制（寄存器重命名），是理解"代码写法如何影响硬件执行"的经典入口，历久弥新。
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作者用寄存器重命名解释清零为何几乎零成本。
作者本人：我想再次强调寄存器重命名有多精妙。它不太好理解，但对乱序处理器至关重要，正是它让清零操作如此高效。x86-64 只有 16 个整数寄存器，却有 100-200 个物理寄存器。每当指令写入 RAX，重命名器就挑一个可用物理寄存器写入，并记录 RAX 现在对应物理寄存器 #137，从而打破依赖链、实现并行。对于清零指令，重命名器直接说"RAX 现在映射到物理寄存器 #0"（专为零值保留），无需任何执行，非常漂亮。
brucedawson查看英文原文
Author here - I just want to drop in to reiterate how awesome register renaming is. It's a bit weird to try and understand, but it is crucial to how these out-of-order processors run, and it is the trick which lets the register zeroing run so efficiently. An x86-64 CPU has sixteen integer registers, but 100-200 physical integer registers. Every time an instruction writes to, say, RAX the renamer chooses an available physical register and does the write to it, recording the fact that RAX is now physical-register #137. This allows the breaking of dependency chains, thus allowing execution parallelism. In the case of the zeroing instructions the register renamer says "RAX now maps to physical-register #0" where that is a register reserved for the purpose of being zero. No execution is needed. It's beautiful. For more details read up on out-of-order execution and register renaming.
追问物理寄存器为何远多于逻辑寄存器。
旧帖作者说过上面那段话。我好奇为什么物理寄存器比逻辑寄存器多这么多。猜测：物理寄存器在硬件上更便宜；增加逻辑寄存器会破坏向后兼容，或至少对按更少寄存器编译的代码没加速；增加逻辑寄存器会给汇编/编译器作者增加复杂度，而增加物理寄存器只是把复杂度转给 CPU 设计者。这些对吗？还有别的原因吗？
philh查看英文原文
Author in the old thread (https://news.ycombinator.com/item?id=19262249) says > An x86-64 CPU has sixteen integer registers, but 100-200 physical integer registers. Every time an instruction writes to, say, RAX the renamer chooses an available physical register and does the write to it, recording the fact that RAX is now physical-register #137. This allows the breaking of dependency chains, thus allowing execution parallelism. I'm curious why they have so many more physical registers than... logical? registers. I have a couple of guesses: * Physical registers are physically cheaper to add than logical registers. * Adding logical registers breaks backwards compatibility, or at best means you get no speedup on things written (/compiled) for fewer logical registers. Adding physical registers lets you improve performance without recompiling. * Adding logical registers increases complexity for people writing assembly and/or compilers. Adding physical registers moves that complexity to people designing CPUs. Are some of these correct? Other reasons I'm missing?
指出 xor 还会影响标志寄存器、也需重命名。
给基准测试点个赞。xor xx,xx 还有一个没提到的复杂点：xor 也会（部分）影响标志寄存器，那部分同样需要被重命名。
superjan查看英文原文
A plus for the benchmarks. One more complication of xor xx,xx goes unmentioned: xor also (partially) affects the flags register. That should get renamed as well.
用 Sandy Bridge 微架构细节解释 4 指令/周期的来源。
关于 4 条指令的限制，见 realworldtech 的 Sandy Bridge 分析。负责清零的寄存器重命名阶段每周期能处理 4 条指令。从 uop 缓存取指后，指令进入 28 项的解码队列（可当小型循环缓冲），然后每周期有 4 个 uop 送往分配/重命名阶段。
rayiner查看英文原文
As to the 4 instruction limit, see: https://www.realworldtech.com/sandy-bridge/5. The register rename stage, which does the zeroing, can handle four instructions per cycle. It’s not immediately obvious from the picture, but after instructions are fetched from the uop cache, they are sent to a 28-entry decoder queue, which can act as a small loop buffer. From there, four uops per cycle are sent to the allocate/rename stage (which is part of the ROB block in the first picture).
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